Techniques herein relate to semiconductor device fabrication. Self-Aligned Patterning (SAP) is a known technique for decreasing feature sizes on semiconductor substrates. Due to the semi conformal nature of spacer materials, however, SAP techniques can lead to undesirable bowing of underlying layers. Techniques herein address such bowing by providing a technique to protect underlying layers while maintaining critical dimensions.
In a typical SAP method, a spacer layer is formed upon mandrels, the top portion of the spacer layer is removed, and then the mandrel is removed, thereby leaving spaced portions of the spacer layer upon an underlying layer. The underlying layer is then etched between the portions of the spacer layer. However, the spacer layer can often have facets, for example, curved or inclined portions. When the underlying layer is subsequently etched, ions deflect from such facets and can impinge upon sidewalls of the underlying layer. As a result, the sidewalls are etched, and the desired vertical profile for etching of the underlying layer is not achieved.